library verilog;
use verilog.vl_types.all;
entity spi_transfer is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        spi_cs          : in     vl_logic;
        spi_sck         : in     vl_logic;
        spi_miso        : out    vl_logic;
        txd_en          : in     vl_logic;
        txd_data        : in     vl_logic_vector(7 downto 0);
        txd_flag        : out    vl_logic
    );
end spi_transfer;
